1. Field of the Invention
The present invention relates generally to output circuits of integrated circuit devices, and more particularly, to an ECL output circuit.
2. Description of the Background Art
With recent progress of a semiconductor technology, a higher speed and higher integration density are required. In order to satisfy such requirements, an emitter coupled logic (hereinafter referred to as an "ECL") circuit is used. An ECL output circuit is used only for a load especially requiring a high speed, while a complementary metal oxide semiconductor (hereinafter referred to as a "CMOS") circuit is used for a circuit which does not require a high speed.
FIG. 12 is a schematic block diagram of a bipolar-CMOS integrated circuit device made in combination of a CMOS logic array circuit and an ECL logic array circuit.
Referring to FIG. 12, an integrated circuit device 200 includes an input circuit 10, an input circuit 20, an internal processing circuit 30, an output circuit 40, and an output circuit 50. Input circuit 10 receives a signal converted to a logic level of the CMOS circuit to provide a j-bit signal to internal processing circuit 30. Input circuit 20 receives a signal converted to a logic level of the ECL circuit to provide a k-bit signal to internal processing circuit 30. Internal processing circuit 30 processes j-bit and k-bit signals from input circuits 10 and 20, respectively, to provide m-bit and n-bit signals to output circuits 40 and 50, respectively. Output circuit 40 converts the m-bit signal to a logic level corresponding to the CMOS circuit to provide the same. Output circuit 50 converts the n-bit signal to a logic level of the ECL circuit to provide the same. The signal converted to the logic level of the CMOS circuit is applied to a circuit providing a signal of a CMOS logic level, for example, a main memory operating at a relatively low speed. The signal of the ECL logic level is applied to a circuit operating at a high speed, for example, a cache memory.
Such an ECL output circuit operating at a high speed is described in FIG. 9 of "A 10k-GATE 950-MHz CML Demonstrator Circuit Made with a 1 .mu.m Trench-Isolated Bipolar Silicon Technology", pp. 552-557, in IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, June 1989, and in FIG. 2 of "A 50-ps 7k-Gate Masterslice Using Mixed Cells Consisting of an NTL Gate and an LCML Macrocell", pp. 202-207, in IEEE Journal of Solid-State Circuits, Vol. SC-22, NO. 2, April 1987.
FIG. 13 is a schematic diagram of a conventional ECL output circuit similar to the ECL circuit described in the aforementioned documents.
An ECL output circuit 50 shown in FIG. 13 includes a constant current source 51, a differential amplifier 52, an output bipolar transistor Q.sub.1, a power supply node V.sub.CC having a first power supply voltage V.sub.CC supplied thereto, a power supply node V.sub.EE having a second power supply voltage V.sub.EE supplied thereto, an output node Do, and input nodes IN, /IN. The output node Do is connected to a terminal voltage V.sub.TT through a terminal resistance R.sub.T. Generally, an ECL output circuit, the power supply node V.sub.CC, the power supply node V.sub.EE, and the terminal voltage V.sub.TT are 0 V, -5.2 V, and -2 V, respectively. The bipolar transistor Q.sub.1 has its collector connected to the power supply node V.sub.CC, its emitter connected to the output node Do, and its base connected to differential amplifier 52. Differential amplifier 52 includes transistors Q.sub.3 and Q.sub.4 and resistances R.sub.1 and R.sub.10. The transistor Q.sub.3 has its collector connected to the power supply node V.sub.CC through the resistance R.sub.10, its emitter connected to constant current source 51, and its base connected to the input node IN. The transistor Q.sub.4 has its collector connected to the power supply node V.sub.CC through the resistance R.sub.1, its emitter connected to constant current source 51, and its base connected to the input node /IN. Operations of the ECL output circuit shown in FIG. 13 will now be described. Input signals IN, /IN are applied to bases of transistors Q.sub.3 and Q.sub.4, respectively, and an output signal is taken out from the emitter of the transistor Q.sub.1.
The case where a signal of a high level is applied to the input node IN and a signal of a low level is applied to the input node /IN will now be considered. Since the transistor Q.sub.3 is turned on in response to the input signal IN and the transistor Q.sub.4 is turned off in response to the input signal /IN, the base of the transistor Q.sub.1 is connected to the power supply node V.sub.CC through the resistance R.sub.1. A path from the power supply node V.sub.CC to the resistance R.sub.1 to the base-emitter of the transistor Q.sub.1 to the output node D.sub.0 is thus configured. A current I.sub.B flows to the base of the transistor Q.sub.1 through the resistance R.sub.1 over the path, whereby an output voltage V.sub.OH of a high level can be obtained at the emitter of the transistor Q.sub.1. The output voltage V.sub.OH is expressed by an equation (1) when V.sub.be represents the base-emitter voltage in the on state of the transistor Q.sub.1 : EQU V.sub.OH =V.sub.CC -R.sub.1 .times.I.sub.B -V.sub.be ( 1)
where V.sub.be is generally 0.7 to 0.8 V.
On the other hand, when a signal of a low level is applied to the input node IN, and a signal of a high level is applied to the input node /IN, the transistor Q.sub.3 is turned off, and the transistor Q.sub.4 is turned on, whereby constant current source 51 is connected to the base of the transistor Q.sub.1. A current I.sub.1 and the base current I.sub.B generated by constant current source 51 flow to the resistance R.sub.1. The output voltage V.sub.OL is given by an equation (2). EQU V.sub.OL =V.sub.CC -R.sub.1 (I.sub.1 +I.sub.B)-V.sub.be ( 2)
The output voltage V.sub.OL is lower than the output V.sub.OH of a high level by R.sub.1 .times.I.sub.1. In the case of the ECL output circuit, R.sub.1 .times.I.sub.1 is approximately 1 V.
As described above, the output signal is changed to V.sub.OL and V.sub.OH according to the level of the input signal.
In the conventional ECL output circuit, differential amplifier 52 is used for applying a suitable potential to the output transistor Q.sub.1. Therefore, even when the output V.sub.OH of a high level is provided, a steady current flows through the transistor Q.sub.3, causing a problem that electric power is continuously consumed. Since a recent semiconductor device has an increased number of output circuits with increase of the amount of information, a large amount of power is consumed as a whole. Therefore, it is necessary to reduce power consumption.
When a current amplification factor hfe of the output transistor Q.sub.1 is not high, it is necessary to obtain a desired output voltage by increasing the base current I.sub.B. However, when the base current I.sub.B is increased, a voltage drop R.sub.1 .times.I.sub.B in providing the high level V.sub.OH is increased. Therefore, it is not possible to obtain V.sub.OH of a sufficiently high level unless the resistance R.sub.1 is decreased. However, when the resistance R.sub.1 is decreased, the voltage drop R.sub.1 (I.sub.B +I.sub.1) in providing the low level V.sub.OL is decreased. Therefore, in order to obtain the low level V.sub.OL of a sufficiently low level, the current I.sub.1 must be increased. Therefore when the current amplification factor hfe is not high, there is a probability that power consumption in providing the low level V.sub.OL is increased.
In order to eliminate the problem, the current amplification factor hfe of the output transistor Q.sub.1 can be increased. However, in order to increase the current amplification factor hfe of the transistor Q.sub.1, it is necessary to control the concentration of impurity precisely, resulting in high costs.